@article{yu2026amma,title={AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving},author={Yu, Zhongkai and Ye, Haotian and Zhou, Chenyang and Venkatachalam, Ohm Rishabh and Pan, Zaifeng and Hu, Zhengding and Kim, Junsung and Ro, Won Woo and Tsai, Po-An and Pei, Shuyi and Kang, Yangwook and Ding, Yufei},journal={arXiv preprint arXiv:2604.26103},year={2026},}
ArXiv
ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
Zhongkai Yu, Chenyang Zhou, Yichen Lin, Hejia Zhang, Haotian Ye, Junxia Cui, Zaifeng Pan, Jishen Zhao, and Yufei Ding
@article{yu2026chipbench,title={ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design},author={Yu, Zhongkai and Zhou, Chenyang and Lin, Yichen and Zhang, Hejia and Ye, Haotian and Cui, Junxia and Pan, Zaifeng and Zhao, Jishen and Ding, Yufei},journal={arXiv preprint arXiv:2601.21448},year={2026},}