Haotian Ye

I am an M.S. student in Computer Engineering at the University of California, San Diego, where I am a research intern in Prof. Yufei Ding’s Lab. My research focuses on efficient AI infrastructure, LLM inference acceleration, hardware-software co-design, and memory-centric architecture.

My recent work explores memory-centric architectures for long-context LLM attention, token-level speculative decoding for diffusion language models, and AI for chip design benchmarks. More broadly, I aim to build efficient and reliable AI infrastructure by co-designing algorithms, runtime systems, memory architectures, and hardware-aware execution strategies for next-generation AI workloads.

Email: h5ye@ucsd.edu

Education

University of California, San Diego (UCSD), 2025 - 2027 (expected)
M.S. in Computer Engineering
Advisor: Prof. Yufei Ding
Sun Yat-Sen University (SYSU), 2021 - 2025
B.E. in Microelectronic Science and Engineering

Experience

Prof. Yufei Ding’s Lab, UCSD, 2025.10 - Present
Research Intern
Xuanyuan Investment Co., Ltd., 2025.06 - 2025.09
Quantitative Research Intern
Hichip Semiconductor Co., Ltd., 2025.02 - 2025.05
Digital Designer Intern
Hardware-Software Co-Design & Parallel Computing Group, SYSU, 2022.06 - 2023.07
Researcher, RISC-V GPGPU Design

news

Apr 28, 2026	Our paper AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving was released on arXiv.
Jan 29, 2026	Our paper ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design was released on arXiv.
Jan 01, 2026	Started working on SimSD: Simple Speculative Decoding in Diffusion Language Models.
Oct 01, 2025	Joined Prof. Yufei Ding’s Lab at UCSD as a research intern.
Sep 01, 2025	Started my M.S. in Computer Engineering at UC San Diego.

Selected Publications

ArXiv

AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving

Zhongkai Yu, Haotian Ye, Chenyang Zhou, Ohm Rishabh Venkatachalam, Zaifeng Pan, Zhengding Hu, Junsung Kim, Won Woo Ro, Po-An Tsai, Shuyi Pei, Yangwook Kang, and Yufei Ding

arXiv preprint arXiv:2604.26103, 2026

arXiv Bib PDF

@article{yu2026amma,
  title = {AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving},
  author = {Yu, Zhongkai and Ye, Haotian and Zhou, Chenyang and Venkatachalam, Ohm Rishabh and Pan, Zaifeng and Hu, Zhengding and Kim, Junsung and Ro, Won Woo and Tsai, Po-An and Pei, Shuyi and Kang, Yangwook and Ding, Yufei},
  journal = {arXiv preprint arXiv:2604.26103},
  year = {2026},
}

ArXiv

ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design

Zhongkai Yu, Chenyang Zhou, Yichen Lin, Hejia Zhang, Haotian Ye, Junxia Cui, Zaifeng Pan, Jishen Zhao, and Yufei Ding

arXiv preprint arXiv:2601.21448, 2026

arXiv Bib PDF

@article{yu2026chipbench,
  title = {ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design},
  author = {Yu, Zhongkai and Zhou, Chenyang and Lin, Yichen and Zhang, Hejia and Ye, Haotian and Cui, Junxia and Pan, Zaifeng and Zhao, Jishen and Ding, Yufei},
  journal = {arXiv preprint arXiv:2601.21448},
  year = {2026},
}