cv
Curriculum Vitae of Haotian Ye.
General Information
| Full Name | Haotian Ye |
| h5ye@ucsd.edu | |
| Affiliation | University of California, San Diego (UCSD) — M.S. Computer Engineering |
| Languages | English, Chinese (Mandarin) |
Education
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2025 - 2027 (expected) M.S. in Computer Engineering
University of California, San Diego (UCSD) - Research intern in Prof. Yufei Ding's Lab.
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2021 - 2025 B.E. in Microelectronic Science and Engineering
Sun Yat-Sen University (SYSU)
Experience
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2025.10 - Present Research Intern
Prof. Yufei Ding's Lab, UC San Diego - Memory-centric architectures for long-context LLM attention serving.
- Block-level speculative decoding for discrete diffusion language models.
- Benchmarks for AI-aided chip design.
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2025.06 - 2025.09 Quantitative Research Intern
Xuanyuan Investment Co., Ltd. -
2025.02 - 2025.05 Digital Designer Intern
Hichip Semiconductor Co., Ltd. -
2022.06 - 2023.07 Researcher (RISC-V GPGPU Design)
Hardware-Software Co-Design & Parallel Computing Group, SYSU
Research Interests
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Efficient AI infrastructure
- LLM inference acceleration
- Memory-centric architecture
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Hardware-software co-design
- Compiler / runtime / architecture full-stack optimization
- AI-aided chip design
Selected Publications
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2026 AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
- Z. Yu, H. Ye, C. Zhou, et al. arXiv:2604.26103.
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2026 ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design
- Z. Yu, C. Zhou, Y. Lin, H. Zhang, H. Ye, et al. arXiv:2601.21448.
Skills
- Hardware: Verilog/SystemVerilog, RISC-V, RTL design, micro-architecture exploration
- Software: Python, C/C++, CUDA
- Domains: LLM inference systems, GPU/accelerator architecture, EDA / AI4Chip