RISC-V GPGPU Design
A RISC-V based GPGPU architecture exploration developed at the SYSU Hardware-Software Co-Design & Parallel Computing Group.
Affiliation: Hardware-Software Co-Design & Parallel Computing Group, Sun Yat-Sen University
Period: 2022.06 - 2023.07
Role: Researcher
Overview
A general-purpose GPU (GPGPU) architecture built on the RISC-V instruction set, exploring how an open ISA can serve as the basis for parallel compute accelerators. Work spanned RTL design, micro-architecture exploration, and toolchain integration for kernel-level workloads.
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